As a slight aside, everything discussed in this column is described in excruciating detail in my book, Bebop to the Boolean Boogie.
Thus, if we can replace our ANDs with NANDs (and our ORs with NORs), our circuit will function faster. In addition to using 4 + 2 = 6 transistors, this means the AND gate (and an OR gate) consists of two stages of delay.
With regard to the previous point, an AND gate is really formed from a NAND gate followed by a NOT gate (similarly, an OR gate consists of a NOR gate followed by a NOT gate).
All of this means that if we can use a NAND or a NOR instead of an AND or an OR, then we can reduce our transistor count by a third. And then we have AND and OR gates, each of which contain six transistors. Next up the complexity ladder are NAND and NOR gates, each of which contain four transistors. Assuming we are talking about CMOS, then a NOT will require two transistors.
If you are designing a printed circuit board (PCB) using simple logic devices, like dual-in-line (DIL) packaged integrated circuits (ICs) containing six NOT gates or four 2-input AND, OR, NAND, or NOR gates, it may be that you end up short of something like an AND gate, but you happen to have a NAND and a NOT gate going spare (or perhaps an OR and three NOTs), in which case your understanding of logic gates can save the day.
It also helps ensure that you understand things like DeMorgan transformations.
Taking a circuit described using AND and OR gates in either a sum-of-products or a product-of-sums format and converting it into an alternative representation using only NAND gates, only NOR gates, or a mixture of NAND and NOR gates is a great way to make sure you understand how the various gates work.
Off the top of my head, I can think of the following reasons for lecturers instructing their students to perform this task: Having said this, thinking back to my own days as a student, it may be best that we don’t actually rule this out as a possible motivation. So, why would a lecturer request that his students implement a logic function using only NAND gates or only NOR gates (note that I specifically didn’t say “only NAND or NOR gates,” because this could be construed to mean that you can use both NANDs and NORs, but not ANDs and ORs etc.)Īlthough students may be surprised to hear this, it’s not necessarily the case that the lecturer is a bitter, frustrated person whose only pleasure in life is to make his or her pupils’ lives more difficult. Why use only NAND gates or only NOR gates? Finally, we will use what we’ve learned to address the student’s initial question. Then we are going to consider the general concepts of translating AND-OR-based circuits into their NAND-NOR counterparts. Next, we’re going to look at this student’s particular poser in more detail, taking it to an initial AND-OR solution. So, what we’re going to do is start by pondering why this class of problem should be posed in the first place.
Finally, he must create an implementation using only NAND gates or only NOR gates.
He’s been told to perform Karnaugh map minimization.
He’s been instructed to create a corresponding truth table.
The student has been presented with a Boolean Equation.
The core of this conundrum is as follows: It’s based on a question that a student posed in the EEWeb forums, and he also sent it directly to yours truly. This is going to be a column that’s divided into three sections. Taking a circuit described using AND and OR gates and converting it into an alternative representation using only NAND or NOR gates is a great way to learn how things work.
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